What is Built-In Self-Test (BIST)

What is Built-In Self-Test (BIST)

Built-In Self-Test (BIST) is a mechanism or system that enables electronic devices and systems to perform self-testing and verification of their internal functionality. It is specifically designed to facilitate efficient and cost-effective testing of ICs during manufacturing.

BIST reduces reliance on external automated test equipment (ATE) by incorporating additional hardware and software features directly into the ICs. This allows the ICs to test their own operation, both functionally and parametrically, using their internal circuits. By performing self-tests, ICs can verify their functionality, identify any potential faults or defects, and ensure reliable performance.

BIST is considered a Design-for-Testability (DFT) technique, as it enhances the ease, speed, efficiency, and cost-effectiveness of electrical testing for chips. It can be implemented in various ways, depending on the specific circuit and product requirements. For example, in the case of DRAMs, a common BIST approach involves incorporating additional circuits on the chip for pattern generation, timing, mode selection, and diagnostic tests.

The development of BIST techniques has been driven by the increasing costs of ATE testing and the growing complexity of integrated circuits. As devices become more intricate, with diverse functional blocks built on different technologies, BIST provides a solution for testing critical circuits that have no direct connections to external pins, such as embedded memories used internally by the devices.

Implementing BIST offers several advantages, including lower test costs by reducing or eliminating the need for external electrical testing using ATE, improved fault coverage by incorporating special test structures onto the chips, shorter test times if BIST can test more structures in parallel, easier customer support, and the ability to perform tests outside the production electrical testing environment.

Potential drawbacks include additional silicon area and fab processing requirements for the BIST circuits, potential impact on access times, additional pin and package size requirements for interfacing with the outside world, and the possibility of incorrect BIST results if the on-chip testing hardware itself fails.